1. Field of the Invention
The present invention relates in general to an ESD protection circuit and method thereof, and more specifically to a high voltage tolerant input/output circuit avoiding damage to N-type MOS transistors from electrostatic discharge (ESD).
2. Description of the Related Art
In the development of the semiconductor manufacture process, dimensions of complementary metal-oxide-semiconductor transistor (CMOS) have reached sub-micron level to upgrade the performance of very large scale integrated (VLSI) circuits and computational speed. As dimensions shrinks, reliability and ESD tolerance of VLSI circuits decline significantly.
ESD models include human-body model (HBM), machine model (MM), and charged-device model (CDM). All three generate instantaneous current of several amperes only for hundreds or even several nanoseconds.
FIG. 1 is a schematic diagram of a conventional high voltage tolerant CMOS VLSI input/output circuit. As shown in FIG. 1, the sources of the PMOS transistors P110-P1n are coupled to the power rail Vcc1, gates of the PMOS transistors P110 and P111 are coupled to the power rail Vcc1, and gates of the PMOS transistors P112-P11n are coupled to pre-driver P1. The drains of the NMOS transistors N110-N11n and the corresponding drains of the PMOS transistors P110-P11n are coupled to a pad 10, and all gates of the NMOS transistors N110-N11n are coupled to the power rail Vcc1. The drains of the NMOS transistors N120-N12n in another row are coupled to the corresponding sources of the NMOS transistors N110-N11n. According to the driving requirement, gates of the NMOS transistors N120 and N121 are connected to the power rail Vss1, and gates of the NMOS transistors N122-N12n are coupled to pre-driver N1. The NMOS transistors N110-N11n and the NMOS transistors N120-N12n are connected in series, and the reliability of the NMOS transistors N120-N12n is enhanced by voltage division. When ESD occurs at the pad 10, the discharge current follows the path of the PMOS transistors P110-P11n, the NMOS transistors N110-N11n, and the NMOS transistors N120-N12n. Because the bias conditions of each transistor differ, current discharge is not even, and some transistors damaged.
The NMOS transistor has an extremely thin gate oxide vulnerable to ESD damage. For example, at the output buffer stage, a commonly used NMOS transistor with a channel width of 300 submicrons can tolerate an ESD voltage of more than 3000 volts if fabricated by conventional 2-submicron manufacture process, and less than 2000 volts if by 1-submicron manufacture process with low-doping-drain (LDD) technology, and about 1000 volts if by 1-submicron manufacture process with LDD and silicide technology. Furthermore, ESD generates an instantaneous discharge current of several amperes in hundreds of nanoseconds. In the high voltage tolerant input/output circuit shown in FIG. 1, the ESD current follows a path of some components only, such that current discharge is uneven and slow, and some components are damaged.